commit 74900633183a28e0cd7c7861d0e51e37b3c16637
parent fd91da0fc82b658706b71bb60862c9c1c9ffbb2c
Author: Bradley Gannon <bradley@bradleygannon.com>
Date: Fri, 28 Nov 2025 22:59:02 -0500
Add packages for major block diagram elements and reorg top level
Diffstat:
7 files changed, 157 insertions(+), 46 deletions(-)
diff --git a/src/main/scala/alu.scala b/src/main/scala/alu.scala
@@ -0,0 +1,15 @@
+package com.rinthyAi.perilus.alu
+
+import chisel3._
+
+class Alu extends Module {
+ val io = IO(new Bundle {
+ val aluControl = Input(UInt(3.W))
+ val srcA, srcB = Input(UInt(32.W))
+
+ val aluResult = Output(UInt(32.W))
+ })
+
+ // TODO implement
+ io.aluResult := 0.U
+}
diff --git a/src/main/scala/control-unit.scala b/src/main/scala/control-unit.scala
@@ -1,46 +0,0 @@
-//> using repository https://central.sonatype.com/repository/maven-snapshots
-//> using scala 2.13.17
-//> using dep org.chipsalliance::chisel:7.3.0
-//> using plugin org.chipsalliance:::chisel-plugin:7.3.0
-//> using options -unchecked -deprecation -language:reflectiveCalls -feature -Xcheckinit
-//> using options -Xfatal-warnings -Ywarn-dead-code -Ywarn-unused -Ymacro-annotations
-
-import chisel3._
-import _root_.circt.stage.ChiselStage
-
-// Figure 7.28 (page 423)
-class ControlUnit extends Module {
- val io = IO(new Bundle {
- val branch, pcUpdate, pcWrite, regWrite, memWrite, irWrite, adrSrc = Output(Bool())
- val resultSrc, aluSrcA, aluSrcB, aluOp, immSrc = Output(UInt(2.W))
- val aluControl = Output(UInt(3.W))
-
- // from datapath
- val op = Input(UInt(7.W))
- val funct3 = Input(UInt(3.W))
- val funct7 = Input(Bool())
- })
-
- io.branch := 0.U
- io.pcUpdate := 0.U
- io.pcWrite := 0.U
- io.regWrite := 0.U
- io.memWrite := 0.U
- io.irWrite := 0.U
- io.adrSrc := 0.U
- io.resultSrc := 0.U
- io.aluSrcA := 0.U
- io.aluSrcB := 0.U
- io.aluOp := 0.U
- io.immSrc := 0.U
- io.aluControl := 0.U
-}
-
-object ControlUnit extends App {
- println(
- ChiselStage.emitSystemVerilogFile(
- new ControlUnit,
- firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info", "-default-layer-specialization=enable")
- )
- )
-}
diff --git a/src/main/scala/controlUnit.scala b/src/main/scala/controlUnit.scala
@@ -0,0 +1,31 @@
+package com.rinthyAi.perilus.controlUnit
+
+import chisel3._
+
+// Figure 7.28 (page 423)
+class ControlUnit extends Module {
+ val io = IO(new Bundle {
+ val op = Input(UInt(7.W))
+ val funct3 = Input(UInt(3.W))
+ val funct7 = Input(Bool())
+
+ val adrSrc, branch, irWrite, memWrite, pcUpdate, pcWrite, regWrite = Output(Bool())
+ val aluSrcA, aluSrcB, aluOp, immSrc, resultSrc = Output(UInt(2.W))
+ val aluControl = Output(UInt(3.W))
+ })
+
+ io.adrSrc := 0.U
+ io.aluControl := 0.U
+ io.aluOp := 0.U
+ io.aluSrcA := 0.U
+ io.aluSrcB := 0.U
+ io.branch := 0.U
+ io.immSrc := 0.U
+ io.irWrite := 0.U
+ io.memWrite := 0.U
+ io.pcUpdate := 0.U
+ io.pcWrite := 0.U
+ io.regWrite := 0.U
+ io.resultSrc := 0.U
+}
+
diff --git a/src/main/scala/extendUnit.scala b/src/main/scala/extendUnit.scala
@@ -0,0 +1,15 @@
+package com.rinthyAi.perilus.extendUnit
+
+import chisel3._
+
+class ExtendUnit extends Module {
+ val io = IO(new Bundle {
+ val input = Input(UInt(21.W))
+ val immSrc = Input(UInt(2.W))
+
+ val immExt = Output(UInt(32.W))
+ })
+
+ // TODO implement
+ io.immExt := 0.U
+}
diff --git a/src/main/scala/main.scala b/src/main/scala/main.scala
@@ -0,0 +1,63 @@
+//> using repository https://central.sonatype.com/repository/maven-snapshots
+//> using scala 2.13.17
+//> using dep org.chipsalliance::chisel:7.3.0
+//> using plugin org.chipsalliance:::chisel-plugin:7.3.0
+//> using options -unchecked -deprecation -language:reflectiveCalls -feature -Xcheckinit
+//> using options -Xfatal-warnings -Ywarn-dead-code -Ywarn-unused -Ymacro-annotations
+
+package com.rinthyAi.perilus.main
+
+import chisel3._
+import _root_.circt.stage.ChiselStage
+
+import com.rinthyAi.perilus.alu._
+import com.rinthyAi.perilus.extendUnit._
+import com.rinthyAi.perilus.memory._
+import com.rinthyAi.perilus.registerFile._
+import com.rinthyAi.perilus.controlUnit._
+
+class Perilus extends Module {
+ val io = IO(new Bundle {})
+
+ val alu = Module(new Alu())
+ val controlUnit = Module(new ControlUnit())
+ val extendUnit = Module(new ExtendUnit())
+ val memory = Module(new Memory())
+ val registerFile = Module(new RegisterFile())
+
+ // TODO connect inputs and outputs
+
+ alu.io.aluControl := 0.U
+ alu.io.srcA := 0.U
+ alu.io.srcB := 0.U
+
+ controlUnit.io.op := 0.U
+ controlUnit.io.funct3 := 0.U
+ controlUnit.io.funct7 := 0.U
+
+ extendUnit.io.input := 0.U
+ extendUnit.io.immSrc := 0.U
+
+ memory.io.address := 0.U
+ memory.io.writeData := 0.U
+ memory.io.writeEnable := 0.U
+
+ registerFile.io.a1 := 0.U
+ registerFile.io.a2 := 0.U
+ registerFile.io.a3 := 0.U
+ registerFile.io.writeData3 := 0.U
+ registerFile.io.writeEnable3 := false.B
+}
+
+object Perilus extends App {
+ println(
+ ChiselStage.emitSystemVerilogFile(
+ new Perilus,
+ firtoolOpts = Array(
+ "-disable-all-randomization",
+ "-strip-debug-info",
+ "-default-layer-specialization=enable"
+ )
+ )
+ )
+}
diff --git a/src/main/scala/memory.scala b/src/main/scala/memory.scala
@@ -0,0 +1,16 @@
+package com.rinthyAi.perilus.memory
+
+import chisel3._
+
+class Memory extends Module {
+ val io = IO(new Bundle {
+ val address = Input(UInt(32.W))
+ val writeData = Input(UInt(32.W))
+ val writeEnable = Input(Bool())
+
+ val readData = Output(UInt(32.W))
+ })
+
+ // TODO implement
+ io.readData := 0.U
+}
diff --git a/src/main/scala/registerFile.scala b/src/main/scala/registerFile.scala
@@ -0,0 +1,17 @@
+package com.rinthyAi.perilus.registerFile
+
+import chisel3._
+
+class RegisterFile extends Module {
+ val io = IO(new Bundle {
+ val a1, a2, a3 = Input(UInt(5.W))
+ val writeData3 = Input(UInt(32.W))
+ val writeEnable3 = Input(Bool())
+
+ val rd1, rd2 = Output(UInt(32.W))
+ })
+
+ // TODO implement
+ io.rd1 := 0.U
+ io.rd2 := 0.U
+}
