commit fd91da0fc82b658706b71bb60862c9c1c9ffbb2c
parent 590c153eef8c995154c2ce721cc8ecca20640ac5
Author: Bradley Gannon <bradley@bradleygannon.com>
Date: Thu, 30 Oct 2025 21:06:18 -0400
Copy parts of chisel-template and add control unit stub
Diffstat:
6 files changed, 126 insertions(+), 0 deletions(-)
diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
@@ -0,0 +1,33 @@
+name: Continuous Integration
+
+on:
+ push:
+ tags: ['*']
+ branches: ['main']
+ pull_request:
+ workflow_dispatch:
+
+jobs:
+ ci:
+ name: ci
+ runs-on: ubuntu-latest
+ steps:
+ - name: Checkout
+ uses: actions/checkout@v4
+ - name: Cleanup
+ run: sed -i "s/%NAME%/test/g" build.mill
+ - name: Cache Scala
+ uses: coursier/cache-action@v6
+ - name: Setup Scala
+ uses: coursier/setup-action@v1
+ with:
+ jvm: adopt:11
+ apps: sbt
+ - name: Setup Dependencies
+ run: |
+ sudo apt-get install verilator
+ verilator --version
+ - name: SBT Test
+ run: sbt test
+ - name: mill Test
+ run: ./mill _.test
diff --git a/.gitignore b/.gitignore
@@ -0,0 +1,10 @@
+*.sv
+*.v
+.bloop
+.bsp
+.metals
+.scala-build
+build
+filelist.f
+project
+target
diff --git a/build.sbt b/build.sbt
@@ -0,0 +1,22 @@
+ThisBuild / scalaVersion := "2.13.17"
+ThisBuild / version := "0.1.0"
+ThisBuild / organization := "%ORGANIZATION%"
+
+val chiselVersion = "7.3.0"
+
+lazy val root = (project in file("."))
+ .settings(
+ name := "%NAME%",
+ libraryDependencies ++= Seq(
+ "org.chipsalliance" %% "chisel" % chiselVersion,
+ "org.scalatest" %% "scalatest" % "3.2.19" % "test",
+ ),
+ scalacOptions ++= Seq(
+ "-language:reflectiveCalls",
+ "-deprecation",
+ "-feature",
+ "-Xcheckinit",
+ "-Ymacro-annotations",
+ ),
+ addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full),
+ )
diff --git a/shell.nix b/shell.nix
@@ -0,0 +1,15 @@
+let
+ nixpkgs = fetchTarball "https://github.com/NixOS/nixpkgs/tarball/nixos-25.05";
+ pkgs = import nixpkgs { config = {}; overlays = []; };
+in
+
+pkgs.mkShellNoCC {
+ packages = with pkgs; [
+ jdk21
+ metals
+ mill
+ sbt
+ scala-cli
+ verilator
+ ];
+}
diff --git a/src/main/scala/control-unit.scala b/src/main/scala/control-unit.scala
@@ -0,0 +1,46 @@
+//> using repository https://central.sonatype.com/repository/maven-snapshots
+//> using scala 2.13.17
+//> using dep org.chipsalliance::chisel:7.3.0
+//> using plugin org.chipsalliance:::chisel-plugin:7.3.0
+//> using options -unchecked -deprecation -language:reflectiveCalls -feature -Xcheckinit
+//> using options -Xfatal-warnings -Ywarn-dead-code -Ywarn-unused -Ymacro-annotations
+
+import chisel3._
+import _root_.circt.stage.ChiselStage
+
+// Figure 7.28 (page 423)
+class ControlUnit extends Module {
+ val io = IO(new Bundle {
+ val branch, pcUpdate, pcWrite, regWrite, memWrite, irWrite, adrSrc = Output(Bool())
+ val resultSrc, aluSrcA, aluSrcB, aluOp, immSrc = Output(UInt(2.W))
+ val aluControl = Output(UInt(3.W))
+
+ // from datapath
+ val op = Input(UInt(7.W))
+ val funct3 = Input(UInt(3.W))
+ val funct7 = Input(Bool())
+ })
+
+ io.branch := 0.U
+ io.pcUpdate := 0.U
+ io.pcWrite := 0.U
+ io.regWrite := 0.U
+ io.memWrite := 0.U
+ io.irWrite := 0.U
+ io.adrSrc := 0.U
+ io.resultSrc := 0.U
+ io.aluSrcA := 0.U
+ io.aluSrcB := 0.U
+ io.aluOp := 0.U
+ io.immSrc := 0.U
+ io.aluControl := 0.U
+}
+
+object ControlUnit extends App {
+ println(
+ ChiselStage.emitSystemVerilogFile(
+ new ControlUnit,
+ firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info", "-default-layer-specialization=enable")
+ )
+ )
+}
diff --git a/src/test/scala/.gitkeep b/src/test/scala/.gitkeep
