perilus

RISC-V processor built with Chisel
git clone https://git.bradleygannon.com/perilus.git
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registerFile.scala (1067B)

      1 package com.rinthyAi.perilus.registerFile
      2 
      3 import chisel3._
      4 import chisel3.util.experimental.loadMemoryFromFile
      5 
      6 class RegisterFile(width: Width, initRegs: String = "", withDebug: Boolean = false) extends Module {
      7   val io = IO(new Bundle {
      8     val a1, a2, a3 = Input(UInt(5.W))
      9     val writeData3 = Input(UInt(width))
     10     val writeEnable3 = Input(Bool())
     11     val rd1, rd2 = Output(UInt(width))
     12     val debug =
     13       if (withDebug) Some(new Bundle {
     14         val reg = Input(UInt(5.W))
     15         val regData = Output(UInt(width))
     16       })
     17       else None
     18   })
     19 
     20   val registerFile = Mem(32, UInt(width))
     21   if (initRegs.nonEmpty) {
     22     loadMemoryFromFile(registerFile, initRegs)
     23   }
     24 
     25   io.debug.foreach(d => {
     26     d.regData := registerFile.read(d.reg)
     27   })
     28 
     29   when(io.a1 === 0.U) {
     30     io.rd1 := 0.U
     31   }.otherwise {
     32     io.rd1 := registerFile.read(io.a1)
     33   }
     34   when(io.a2 === 0.U) {
     35     io.rd2 := 0.U
     36   }.otherwise {
     37     io.rd2 := registerFile.read(io.a2)
     38   }
     39 
     40   when(io.writeEnable3 && io.a3 =/= 0.U && !reset.asBool) {
     41     registerFile.write(io.a3, io.writeData3)
     42   }
     43 }