perilus

RISC-V processor built with Chisel
git clone https://git.bradleygannon.com/perilus.git
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alu.scala (1827B)


      1 package com.rinthyAi.perilus.alu
      2 
      3 import chisel3._
      4 import chisel3.util._
      5 
      6 class Alu extends Module {
      7   val io = IO(new Bundle {
      8     val aluControl = Input(AluControl())
      9     val srcA, srcB = Input(UInt(32.W))
     10     val aluResult = Output(UInt(32.W))
     11     val zero, lessThan = Output(Bool())
     12   })
     13 
     14   io.aluResult := 0.U
     15   io.zero := false.B
     16   io.lessThan := false.B
     17 
     18   val srcBShift = WireInit(0.U)
     19   when(io.srcB(5)) {
     20     srcBShift := 32.U
     21   }.otherwise {
     22     srcBShift := io.srcB(4, 0)
     23   }
     24 
     25   switch(io.aluControl) {
     26     is(AluControl.add) {
     27       io.aluResult := io.srcA + io.srcB
     28     }
     29     is(AluControl.sub) {
     30       io.aluResult := io.srcA - io.srcB
     31       io.zero := io.aluResult === 0.U
     32     }
     33     is(AluControl.sll) {
     34       io.aluResult := io.srcA << srcBShift
     35     }
     36     is(AluControl.slt) {
     37       io.aluResult := (io.srcA.asSInt < io.srcB.asSInt).asUInt
     38       io.lessThan := io.aluResult === 1.U
     39     }
     40     is(AluControl.sltu) {
     41       io.aluResult := io.srcA < io.srcB
     42       io.lessThan := io.aluResult === 1.U
     43     }
     44     is(AluControl.xor) {
     45       io.aluResult := io.srcA ^ io.srcB
     46     }
     47     is(AluControl.srl) {
     48       io.aluResult := io.srcA >> srcBShift
     49     }
     50     is(AluControl.sra) {
     51       io.aluResult := (io.srcA.asSInt >> srcBShift).asUInt
     52     }
     53     is(AluControl.or) {
     54       io.aluResult := io.srcA | io.srcB
     55     }
     56     is(AluControl.and) {
     57       io.aluResult := io.srcA & io.srcB
     58     }
     59   }
     60 }
     61 
     62 object AluControl extends ChiselEnum {
     63   val add, sub, sll, slt, sltu, xor, srl, sra, or, and = Value
     64 }
     65 
     66 object AluSrcA extends ChiselEnum {
     67   val pc, oldPc, rd1 = Value
     68 }
     69 
     70 object AluSrcB extends ChiselEnum {
     71   val rd2, immExt, four = Value
     72 }
     73 
     74 object AluOp extends ChiselEnum {
     75   val memory, branch, arithmetic, auipc = Value
     76 }
     77 
     78 object ResultSrc extends ChiselEnum {
     79   val aluOutBuf, readDataBuf, aluResult, immExt = Value
     80 }