README.md (1351B)
1 # `perilus` 2 3 A [RISC-V RV32I] processor written with [Chisel] as a learning exercise. Basically the same design 4 as the multi-cycle processor from [Harris and Harris], but extended to cover the entire base 5 instruction set. 6 7 [RISC-V RV32I]: https://docs.riscv.org/reference/isa/unpriv/rv32.html 8 [Chisel]: https://www.chisel-lang.org/docs 9 [Harris and Harris]: https://www.bookfinder.com/search/?ac=sl&st=sl&ref=bf_s2_a1_t1_1&qi=zIR9Gre1QrCSsNJWIGHNSdC.6mo_1761953030_1:42:250&bq=author%3Dsarah%2520harris%253B%2520david%2520harris%26title%3Ddigital%2520design%2520and%2520computer%2520architecture%252C%2520risc%2Dv%2520edition%2520risc%2Dv 10 11 ## Usage 12 13 1. Install dependencies[^nix] 14 - [Scala 2] (**not 3** because Chisel isn't compatible with it) 15 - [`sbt`] 16 - [Verilator] 17 - [`just`] 18 - [Rust] 19 1. `just test chisel verilate simulate` 20 21 [Scala 2]: https://www.scala-lang.org/download/all.html 22 [`sbt`]: https://www.scala-sbt.org/ 23 [Verilator]: https://verilator.org/guide/latest/overview.html 24 [`just`]: https://github.com/casey/just 25 [Rust]: https://rustup.rs/ 26 27 The controls for the standalone simulator aren't documented yet, but the source code makes them at 28 least mildly clear. `vim` users will feel somewhat at home. 29 30 [^nix]: If you use the `nix` package manager, you can use the `shell.nix` file in the project root 31 with `nix-shell`.