perilus

RISC-V processor built with Chisel
git clone https://git.bradleygannon.com/perilus.git
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extendUnit.scala (1063B)

      1 package com.rinthyAi.perilus.extendUnit
      2 
      3 import chisel3._
      4 import chisel3.util._
      5 
      6 class ExtendUnit extends Module {
      7   val io = IO(new Bundle {
      8     val input = Input(UInt(25.W))
      9     val immSrc = Input(ImmSrc())
     10     val immExt = Output(UInt(32.W))
     11   })
     12 
     13   io.immExt := 0.U
     14 
     15   // Table 7.5 (page 412)
     16   switch(io.immSrc) {
     17     is(ImmSrc.iType) {
     18       io.immExt := Cat(Fill(20, io.input(24)), io.input(24, 13))
     19     }
     20     is(ImmSrc.sType) {
     21       io.immExt := Cat(Fill(20, io.input(24)), io.input(24, 18), io.input(4, 0))
     22     }
     23     is(ImmSrc.bType) {
     24       io.immExt := Cat(
     25         Fill(20, io.input(24)),
     26         io.input(0),
     27         io.input(23, 18),
     28         io.input(4, 1),
     29         0.U(1.W)
     30       )
     31     }
     32     is(ImmSrc.jType) {
     33       io.immExt := Cat(
     34         Fill(12, io.input(24)),
     35         io.input(12, 5),
     36         io.input(13),
     37         io.input(23, 14),
     38         0.U(1.W)
     39       )
     40     }
     41     is(ImmSrc.uType) {
     42       io.immExt := Cat(io.input(24, 5), Fill(12, 0.U))
     43     }
     44   }
     45 }
     46 
     47 object ImmSrc extends ChiselEnum {
     48   val iType, sType, bType, jType, uType = Value
     49 }