perilus

commit 96a96ed223967caaf5d896b312a457807a84aeee
parent 48e5ea4c46cf0cb011d9519e0eefeb80f5cbf10d
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Tue, 27 Jan 2026 21:03:27 -0500

Remove printf debug statements

Diffstat:
M
src/main/scala/alu.scala
 | 
1
-
M
src/main/scala/controlUnit.scala
 | 
1
-
M
src/main/scala/main.scala
 | 
6
------

3 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/src/main/scala/alu.scala b/src/main/scala/alu.scala
@@ -15,7 +15,6 @@ class Alu extends Module {
 
   switch(io.aluControl) {
     is(AluControl.add) {
-      printf(cf"srcA = ${io.srcA}, srcB = ${io.srcB}\n")
       io.aluResult := io.srcA + io.srcB
     }
     is(AluControl.sub) {
diff --git a/src/main/scala/controlUnit.scala b/src/main/scala/controlUnit.scala
@@ -46,7 +46,6 @@ class ControlUnit(withDebug: Boolean = false) extends Module {
   io.resultSrc := ResultSrc.aluOutBuf
 
   // Main FSM (Figure 7.45, page 436)
-  printf(cf"state = $state\n")
   switch(state) {
     is(ControlUnitState.fetch) {
       io.adrSrc := false.B
diff --git a/src/main/scala/main.scala b/src/main/scala/main.scala
@@ -93,8 +93,6 @@ class Perilus(
   val aluOutBuf = RegInit(0.U(width))
   aluOutBuf := alu.io.aluResult
 
-  printf(cf"aluOutBuf = $aluOutBuf\n")
-
   val result = WireDefault(0.U(width))
   pcNext := result
   switch(controlUnit.io.resultSrc) {
@@ -157,10 +155,6 @@ class Perilus(
   io.registerFile.io.a3 := instr(11, 7)
   io.registerFile.io.writeData3 := result
   io.registerFile.io.writeEnable3 := controlUnit.io.regWrite
-
-  printf("----\n")
-  printf(cf"pcNext = $pcNext\n")
-  printf(cf"pc = $pc\n")
 }
 
 object Perilus extends App {