perilus

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commit 48e5ea4c46cf0cb011d9519e0eefeb80f5cbf10d
parent 5504dfd4612fcbc03dfa4be2656e512c94a08dab
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Tue, 27 Jan 2026 21:01:03 -0500

Make memory addresses byte-oriented with rounding to word boundaries

Diffstat:
Msrc/main/scala/memory.scala | 14+++++---------
Msrc/test/scala/perilus/memory.scala | 4++--
2 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/src/main/scala/memory.scala b/src/main/scala/memory.scala @@ -23,24 +23,20 @@ class Memory( else None }) + private val AddressShift = log2Ceil(width.get / 8) + val memory = Mem(numWords, UInt(width)) if (initMem.nonEmpty) { loadMemoryFromFile(memory, initMem) } - // this fixes warnings related to width being too high or low to index memory - // see https://www.chisel-lang.org/docs/cookbooks/cookbook#how-do-i-resolve-dynamic-index--is-too-widenarrow-for-extractee- - val correctWidth = log2Ceil(numWords) - val correctWidthAddress = io.address.pad(correctWidth)(correctWidth - 1, 0) - io.debug.foreach(d => { - val correctWidthDebugAddress = d.memAddr.pad(correctWidth)(correctWidth - 1, 0) - d.memData := memory.read(correctWidthDebugAddress) + d.memData := memory.read(d.memAddr >> AddressShift) }) when(io.writeEnable) { - memory.write(correctWidthAddress, io.writeData) + memory.write(io.address >> AddressShift, io.writeData) } - io.readData := memory.read(correctWidthAddress) + io.readData := memory.read(io.address >> AddressShift) } diff --git a/src/test/scala/perilus/memory.scala b/src/test/scala/perilus/memory.scala @@ -10,8 +10,8 @@ class MemoryTests extends AnyFunSpec with ChiselSim { simulate(new Memory(8, 32.W, System.getProperty("user.dir") + "/assets/mem-zeros-8x32.hex")) { memory => { - val addr1 = "h12e".U - val addr2 = "h0d7".U + val addr1 = "h4".U + val addr2 = "h18".U val data1 = "he7d857de".U val data2 = "h38cc122f".U