perilus

commit 8aa667db929660c69bf2e38f80b44a9840966dfd
parent 391e8e6e9a56ff0bf016dbd483eacc3d8ac5b9ec
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Wed, 28 Jan 2026 16:06:02 -0500

Dynamically write memory files for tests instead of keeping them in assets/

Diffstat:
D
assets/mem-beq-64x32.hex
 | 
64
----------------------------------------------------------------
D
assets/mem-lw-64x32.hex
 | 
64
----------------------------------------------------------------
D
assets/mem-sw-64x32.hex
 | 
64
----------------------------------------------------------------
D
assets/reg-beq-x32.hex
 | 
32
--------------------------------
D
assets/reg-lw-x32.hex
 | 
32
--------------------------------
D
assets/reg-sw-x32.hex
 | 
32
--------------------------------
M
src/test/scala/perilus/alu.scala
 | 
2
++
M
src/test/scala/perilus/controlUnit.scala
 | 
2
++
M
src/test/scala/perilus/extendUnit.scala
 | 
2
++
M
src/test/scala/perilus/main.scala
 | 
76
++++++++++++++++++++++++++++++++++++++++++++++++----------------------------
M
src/test/scala/perilus/memory.scala
 | 
7
++++++-
M
src/test/scala/perilus/registerFile.scala
 | 
2
++
A
src/test/scala/perilus/utils.scala
 | 
26
++++++++++++++++++++++++++

13 files changed, 88 insertions(+), 317 deletions(-)
diff --git a/assets/mem-beq-64x32.hex b/assets/mem-beq-64x32.hex
@@ -1,64 +0,0 @@
-02618563
-00930863
-5ee7809a
-947924f4
-fc24525a
-6c858974
-4996dd8c
-50415755
-b329e2c1
-99a84ca8
-ca029ae4
-a57954e9
-a7b0a4b1
-5f1c57ea
-bab5ee54
-e63aec6d
-7afaad60
-334c7d51
-bc83bea3
-63b83aab
-e1940fda
-4812b9fa
-7c224e0a
-305c08cc
-85e21635
-6e0cd50c
-d976069b
-f7f1ab0f
-24d8e524
-0f15069c
-1fa3eed3
-f73d90fa
-bd46aca5
-a519ad77
-70cd4ed3
-a722ba58
-cec41109
-9955f8a8
-ba5eb4f8
-cb32fd9d
-4f3fc791
-43bcbe26
-c1600d35
-0b5fc381
-dddfa0c3
-0331db73
-1e088fee
-9a0cdee4
-29580f62
-043925f7
-653647af
-d5e9eb13
-3e559887
-f098fa6f
-0f3f9400
-07163d81
-b37a3f8e
-0c11b791
-b3fa9fcf
-9d6ae141
-a34ef0d5
-3e850e1a
-2a410325
-8fce4057
diff --git a/assets/mem-lw-64x32.hex b/assets/mem-lw-64x32.hex
@@ -1,64 +0,0 @@
-0a85aa83
-b88829b6
-5ee7809a
-947924f4
-fc24525a
-6c858974
-4996dd8c
-50415755
-b329e2c1
-99a84ca8
-ca029ae4
-a57954e9
-a7b0a4b1
-5f1c57ea
-bab5ee54
-e63aec6d
-7afaad60
-334c7d51
-bc83bea3
-63b83aab
-e1940fda
-4812b9fa
-7c224e0a
-305c08cc
-85e21635
-6e0cd50c
-d976069b
-f7f1ab0f
-24d8e524
-0f15069c
-1fa3eed3
-f73d90fa
-bd46aca5
-a519ad77
-70cd4ed3
-a722ba58
-cec41109
-9955f8a8
-ba5eb4f8
-cb32fd9d
-4f3fc791
-43bcbe26
-c1600d35
-0b5fc381
-dddfa0c3
-0331db73
-1e088fee
-9a0cdee4
-29580f62
-043925f7
-653647af
-d5e9eb13
-3e559887
-f098fa6f
-0f3f9400
-07163d81
-b37a3f8e
-0c11b791
-b3fa9fcf
-9d6ae141
-a34ef0d5
-3e850e1a
-2a410325
-8fce4057
diff --git a/assets/mem-sw-64x32.hex b/assets/mem-sw-64x32.hex
@@ -1,64 +0,0 @@
-fe64ae23
-b88829b6
-5ee7809a
-947924f4
-fc24525a
-6c858974
-4996dd8c
-50415755
-b329e2c1
-99a84ca8
-ca029ae4
-a57954e9
-a7b0a4b1
-5f1c57ea
-bab5ee54
-e63aec6d
-7afaad60
-334c7d51
-bc83bea3
-63b83aab
-e1940fda
-4812b9fa
-7c224e0a
-305c08cc
-85e21635
-6e0cd50c
-d976069b
-f7f1ab0f
-24d8e524
-0f15069c
-1fa3eed3
-f73d90fa
-bd46aca5
-a519ad77
-70cd4ed3
-a722ba58
-cec41109
-9955f8a8
-ba5eb4f8
-cb32fd9d
-4f3fc791
-43bcbe26
-c1600d35
-0b5fc381
-dddfa0c3
-0331db73
-1e088fee
-9a0cdee4
-29580f62
-043925f7
-653647af
-d5e9eb13
-3e559887
-f098fa6f
-0f3f9400
-07163d81
-b37a3f8e
-0c11b791
-b3fa9fcf
-9d6ae141
-a34ef0d5
-3e850e1a
-2a410325
-8fce4057
diff --git a/assets/reg-beq-x32.hex b/assets/reg-beq-x32.hex
@@ -1,32 +0,0 @@
-00000000
-00000000
-00000000
-abcdef01
-00000000
-00000000
-abcde012
-00000000
-00000000
-abcde012
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
diff --git a/assets/reg-lw-x32.hex b/assets/reg-lw-x32.hex
@@ -1,32 +0,0 @@
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000030
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
diff --git a/assets/reg-sw-x32.hex b/assets/reg-sw-x32.hex
@@ -1,32 +0,0 @@
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-01830169
-00000000
-00000000
-00000038
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
diff --git a/src/test/scala/perilus/alu.scala b/src/test/scala/perilus/alu.scala
@@ -1,3 +1,5 @@
+package com.rinthyAi.perilus.test.alu
+
 import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import org.scalatest.funspec.AnyFunSpec
diff --git a/src/test/scala/perilus/controlUnit.scala b/src/test/scala/perilus/controlUnit.scala
@@ -1,3 +1,5 @@
+package com.rinthyAi.perilus.test.controlUnit
+
 import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import org.scalatest.funspec.AnyFunSpec
diff --git a/src/test/scala/perilus/extendUnit.scala b/src/test/scala/perilus/extendUnit.scala
@@ -1,3 +1,5 @@
+package com.rinthyAi.perilus.test.extendUnit
+
 import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import org.scalatest.funspec.AnyFunSpec
diff --git a/src/test/scala/perilus/main.scala b/src/test/scala/perilus/main.scala
@@ -1,31 +1,39 @@
+package com.rinthyAi.perilus.test.main
+
 import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import org.scalatest.funspec.AnyFunSpec
 import scala.collection.mutable.ArrayBuffer
 
 import com.rinthyAi.perilus.main._
+import com.rinthyAi.perilus.test.utils.TestUtils.initMemFile
 
 class PerilusTests extends AnyFunSpec with ChiselSim {
   describe("Perilus") {
     it("executes lw") {
+      val rd = 21
+      val rs1 = 11
+      val base = 0x30
+      val imm = 0xa8
+      val memAddr = base + imm
+      val memData = 0x0f3f9400
+
+      var registerFile = ArrayBuffer.fill(32)(0x00000000)
+      registerFile(rs1) = 0x00000030
+      var memory = ArrayBuffer.fill(64)(0x00000000)
+      memory(0) = 0x0a85aa83 // lw x21, 0xa8(x11)
+      memory(memAddr / 4) = memData
+
       simulate(
         new Perilus(
-          initRegs = System.getProperty("user.dir") + "/assets/reg-lw-x32.hex",
-          initMem = System.getProperty("user.dir") + "/assets/mem-lw-64x32.hex",
+          initRegs = initMemFile(registerFile),
+          initMem = initMemFile(memory),
           withDebug = true
         )
       ) { perilus =>
         {
           val perilusDebug = perilus.io.debug.get
 
-          // lw x21, 0xa8(x11)
-          val rd = 21
-          val rs1 = 11
-          val base = 0x30
-          val imm = 0xa8
-          val memAddr = (base + imm).U
-          val memData = 0x0f3f9400
-
           // rs1 contains the base pointer
           perilusDebug.reg.poke(rs1)
           perilusDebug.regData.expect(base)
@@ -52,25 +60,29 @@ class PerilusTests extends AnyFunSpec with ChiselSim {
       }
     }
     it("executes sw") {
+      val rs1 = 9
+      val rs2 = 6
+      val base = 0x38
+      val imm = -4
+      val memAddr = base + imm
+      val memData = 0x01830169
+
+      var registerFile = ArrayBuffer.fill(32)(0x00000000)
+      registerFile(rs1) = base
+      registerFile(rs2) = memData
+      var memory = ArrayBuffer.fill(64)(0x00000000)
+      memory(0) = 0xfe64ae23 // sw x6, -4(x9)
+
       simulate(
         new Perilus(
-          initRegs = System.getProperty("user.dir") + "/assets/reg-sw-x32.hex",
-          initMem = System.getProperty("user.dir") + "/assets/mem-sw-64x32.hex",
+          initRegs = initMemFile(registerFile),
+          initMem = initMemFile(memory),
           withDebug = true
         )
       ) { perilus =>
         {
           val perilusDebug = perilus.io.debug.get
 
-          // sw x6, -4(x9)
-          // sw rs2, imm(rs1)
-          val rs2 = 6
-          val rs1 = 9
-          val base = 0x38
-          val imm = -4
-          val memAddr = (base + imm).U
-          val memData = 0x01830169
-
           // rs1 contains the base pointer
           perilusDebug.reg.poke(rs1)
           perilusDebug.regData.expect(base)
@@ -93,21 +105,29 @@ class PerilusTests extends AnyFunSpec with ChiselSim {
       }
     }
     it("executes beq") {
+      val rs1 = 3
+      val rs2 = 6
+      val rs3 = 9
+      val offset = 16.U
+
+      var registerFile = ArrayBuffer.fill(32)(0x00000000)
+      registerFile(rs1) = 0xabcdef01
+      registerFile(rs2) = 0xabcde012
+      registerFile(rs3) = 0xabcde012
+      var memory = ArrayBuffer.fill(64)(0x00000000)
+      memory(0) = 0x02618563 // beq x3, x6, 0x4
+      memory(1) = 0x00930863 // beq x6, x9, 0x4
+
       simulate(
         new Perilus(
-          initRegs = System.getProperty("user.dir") + "/assets/reg-beq-x32.hex",
-          initMem = System.getProperty("user.dir") + "/assets/mem-beq-64x32.hex",
+          initRegs = initMemFile(registerFile),
+          initMem = initMemFile(memory),
           withDebug = true
         )
       ) { perilus =>
         {
           val perilusDebug = perilus.io.debug.get
 
-          val rs1 = 3
-          val rs2 = 6
-          val rs3 = 9
-          val offset = 16.U
-
           // Verify that registers are/aren't equal as expected
           perilusDebug.reg.poke(rs1)
           val rs1_t = perilusDebug.regData.peek()
diff --git a/src/test/scala/perilus/memory.scala b/src/test/scala/perilus/memory.scala
@@ -1,13 +1,18 @@
+package com.rinthyAi.perilus.test.memory
+
 import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import org.scalatest.funspec.AnyFunSpec
+import scala.collection.mutable.ArrayBuffer
 
 import com.rinthyAi.perilus.memory._
+import com.rinthyAi.perilus.test.utils.TestUtils.initMemFile
 
 class MemoryTests extends AnyFunSpec with ChiselSim {
   describe("Memory") {
     it("stores and retrieves data") {
-      simulate(new Memory(8, 32.W, System.getProperty("user.dir") + "/assets/mem-zeros-8x32.hex")) {
+      val numWords = 8
+      simulate(new Memory(numWords, 32.W, initMemFile(ArrayBuffer.fill(numWords)(0x00000000)))) {
         memory =>
           {
             val addr1 = "h4".U
diff --git a/src/test/scala/perilus/registerFile.scala b/src/test/scala/perilus/registerFile.scala
@@ -1,3 +1,5 @@
+package com.rinthyAi.perilus.test.registerFile
+
 import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import org.scalatest.funspec.AnyFunSpec
diff --git a/src/test/scala/perilus/utils.scala b/src/test/scala/perilus/utils.scala
@@ -0,0 +1,26 @@
+package com.rinthyAi.perilus.test.utils
+
+import java.nio.charset.StandardCharsets
+import java.nio.file.{Files, Path, StandardOpenOption}
+import scala.collection.mutable.ArrayBuffer
+
+object TestUtils {
+  def initMemFile(data: ArrayBuffer[Int]): String = {
+    val tmp: Path = Files.createTempFile("mem_", ".hex")
+
+    val sb = new StringBuilder
+    var i = 0
+    while (i < data.length) {
+      sb.append(String.format("%08x", java.lang.Integer.toUnsignedLong(data(i)))).append('\n')
+      i += 1
+    }
+
+    Files.write(
+      tmp,
+      sb.toString.getBytes(StandardCharsets.US_ASCII),
+      StandardOpenOption.TRUNCATE_EXISTING
+    )
+
+    tmp.toAbsolutePath.toString
+  }
+}