perilus

RISC-V processor built with Chisel
git clone https://git.bradleygannon.com/perilus.git
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registerFile.scala (2318B)

      1 package com.rinthyAi.perilus.test.registerFile
      2 
      3 import chisel3._
      4 import chisel3.simulator.scalatest.ChiselSim
      5 import org.scalatest.funspec.AnyFunSpec
      6 import scala.collection.mutable.ArrayBuffer
      7 
      8 import com.rinthyAi.perilus.registerFile._
      9 import com.rinthyAi.perilus.test.utils.TestUtils.initMemFile
     10 
     11 class RegisterFileTests extends AnyFunSpec with ChiselSim {
     12   describe("RegisterFile") {
     13     it("stores and retrieves data") {
     14       simulate(
     15         new RegisterFile(32.W, initMemFile(ArrayBuffer.fill(32)(0x00000000)))
     16       ) { registerFile =>
     17         {
     18           val reg1 = 5.U
     19           val reg2 = 19.U
     20           val reg3 = 16.U
     21           val data1 = "ha342aa0a".U
     22           val data2 = "h3361a296".U
     23 
     24           registerFile.io.a1.poke(reg1)
     25           registerFile.io.a2.poke(reg2)
     26           registerFile.io.a3.poke(reg3)
     27 
     28           registerFile.io.rd1.expect(0.U)
     29           registerFile.io.rd2.expect(0.U)
     30 
     31           registerFile.io.writeData3.poke(data1)
     32           registerFile.io.writeEnable3.poke(true.B)
     33 
     34           registerFile.clock.step(1)
     35 
     36           registerFile.io.a1.poke(reg3)
     37           registerFile.io.rd1.expect(data1)
     38           registerFile.io.a3.poke(reg2)
     39           registerFile.io.writeData3.poke(data2)
     40 
     41           registerFile.clock.step(1)
     42 
     43           registerFile.io.a2.poke(reg2)
     44           registerFile.io.rd2.expect(data2)
     45 
     46           registerFile.io.writeEnable3.poke(false.B)
     47           registerFile.clock.step(1)
     48           registerFile.io.rd2.expect(data2)
     49         }
     50       }
     51     }
     52     it("always reads zero on x0") {
     53       simulate(
     54         new RegisterFile(32.W, initMemFile(ArrayBuffer.fill(32)(0xffffffff)))
     55       ) { registerFile =>
     56         {
     57           registerFile.io.a1.poke(0.U)
     58           registerFile.io.rd1.expect(0.U)
     59           registerFile.io.a2.poke(0.U)
     60           registerFile.io.rd2.expect(0.U)
     61         }
     62       }
     63     }
     64     it("doesn't write to x0") {
     65       simulate(
     66         new RegisterFile(32.W, initMemFile(ArrayBuffer.fill(32)(0x00000000)))
     67       ) { registerFile =>
     68         {
     69           registerFile.io.a3.poke(0.U)
     70           registerFile.io.writeData3.poke("h500bc902".U)
     71           registerFile.io.writeEnable3.poke(true.B)
     72           registerFile.clock.step(1)
     73           registerFile.io.a1.poke(0.U)
     74           registerFile.io.rd1.expect(0.U)
     75         }
     76       }
     77     }
     78   }
     79 }