perilus

commit 391e8e6e9a56ff0bf016dbd483eacc3d8ac5b9ec
parent d0b8e7209bf46d7e010fc4b1ae861d7ba80340b6
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Tue, 27 Jan 2026 21:20:31 -0500

Move generated Verilog files into their own directory

Diffstat:
M
src/main/scala/main.scala
 | 
1
+

1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/src/main/scala/main.scala b/src/main/scala/main.scala
@@ -161,6 +161,7 @@ object Perilus extends App {
   println(
     ChiselStage.emitSystemVerilogFile(
       new Perilus,
+      args = Array("--target-dir", "generated"),
       firtoolOpts = Array(
         "-disable-all-randomization",
         "-strip-debug-info",