perilus

commit 5dff292b4f84ec974004621883b28fadf504d849
parent 5ce26af2c37730a9add3aed54e82824f67aa7e4b
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Sun, 30 Nov 2025 13:32:04 -0500

Implement RegisterFile

Diffstat:
M
src/main/scala/main.scala
 | 
7
+++++--
M
src/main/scala/registerFile.scala
 | 
17
+++++++++++------
A
src/test/scala/perilus/registerFile.scala
 | 
59
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

3 files changed, 75 insertions(+), 8 deletions(-)
diff --git a/src/main/scala/main.scala b/src/main/scala/main.scala
@@ -19,11 +19,14 @@ import com.rinthyAi.perilus.controlUnit._
 class Perilus extends Module {
   val io = IO(new Bundle {})
 
+  val width = 32.W
+  val memorySizeWords = 1024
+
   val alu = Module(new Alu())
   val controlUnit = Module(new ControlUnit())
   val extendUnit = Module(new ExtendUnit())
-  val memory = Module(new Memory(1024, 32.W))
-  val registerFile = Module(new RegisterFile())
+  val memory = Module(new Memory(memorySizeWords, width))
+  val registerFile = Module(new RegisterFile(width))
 
   // TODO connect inputs and outputs
 
diff --git a/src/main/scala/registerFile.scala b/src/main/scala/registerFile.scala
@@ -2,16 +2,21 @@ package com.rinthyAi.perilus.registerFile
 
 import chisel3._
 
-class RegisterFile extends Module {
+class RegisterFile(width: Width) extends Module {
   val io = IO(new Bundle {
     val a1, a2, a3 = Input(UInt(5.W))
-    val writeData3 = Input(UInt(32.W))
+    val writeData3 = Input(UInt(width))
     val writeEnable3 = Input(Bool())
 
-    val rd1, rd2 = Output(UInt(32.W))
+    val rd1, rd2 = Output(UInt(width))
   })
 
-  // TODO implement
-  io.rd1 := 0.U
-  io.rd2 := 0.U
+  val registerFile = RegInit(VecInit(Seq.fill(32)(0.U(width))))
+
+  io.rd1 := registerFile(io.a1)
+  io.rd2 := registerFile(io.a2)
+
+  when(io.writeEnable3 && io.a3 =/= 0.U) {
+    registerFile(io.a3) := io.writeData3
+  }
 }
diff --git a/src/test/scala/perilus/registerFile.scala b/src/test/scala/perilus/registerFile.scala
@@ -0,0 +1,59 @@
+import chisel3._
+import chisel3.simulator.scalatest.ChiselSim
+import org.scalatest.funspec.AnyFunSpec
+
+import com.rinthyAi.perilus.registerFile._
+
+class RegisterFileTests extends AnyFunSpec with ChiselSim {
+  describe("RegisterFile") {
+    it("stores and retrieves data") {
+      simulate(new RegisterFile(32.W)) { registerFile =>
+        {
+          val reg1 = 5.U
+          val reg2 = 19.U
+          val reg3 = 16.U
+          val data1 = "ha342aa0a".U
+          val data2 = "h3361a296".U
+
+          registerFile.io.a1.poke(reg1)
+          registerFile.io.a2.poke(reg2)
+          registerFile.io.a3.poke(reg3)
+
+          registerFile.io.rd1.expect(0.U)
+          registerFile.io.rd2.expect(0.U)
+
+          registerFile.io.writeData3.poke(data1)
+          registerFile.io.writeEnable3.poke(true.B)
+
+          registerFile.clock.step(1)
+
+          registerFile.io.a1.poke(reg3)
+          registerFile.io.rd1.expect(data1)
+          registerFile.io.a3.poke(reg2)
+          registerFile.io.writeData3.poke(data2)
+
+          registerFile.clock.step(1)
+
+          registerFile.io.a2.poke(reg2)
+          registerFile.io.rd2.expect(data2)
+
+          registerFile.io.writeEnable3.poke(false.B)
+          registerFile.clock.step(1)
+          registerFile.io.rd2.expect(data2)
+        }
+      }
+    }
+    it("doesn't write to x0") {
+      simulate(new RegisterFile(32.W)) { registerFile =>
+        {
+          registerFile.io.a3.poke(0.U)
+          registerFile.io.writeData3.poke("h500bc902".U)
+          registerFile.io.writeEnable3.poke(true.B)
+          registerFile.clock.step(1)
+          registerFile.io.a1.poke(0.U)
+          registerFile.io.rd1.expect(0.U)
+        }
+      }
+    }
+  }
+}