perilus

RISC-V processor built with Chisel
git clone https://git.bradleygannon.com/perilus.git
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build.sbt (653B)

      1 ThisBuild / scalaVersion     := "2.13.18"
      2 ThisBuild / version          := "0.1.0"
      3 ThisBuild / organization     := "%ORGANIZATION%"
      4 
      5 val chiselVersion = "7.7.0"
      6 
      7 lazy val root = (project in file("."))
      8   .settings(
      9     name := "%NAME%",
     10     libraryDependencies ++= Seq(
     11       "org.chipsalliance" %% "chisel" % chiselVersion,
     12       "org.scalatest" %% "scalatest" % "3.2.19" % "test",
     13     ),
     14     scalacOptions ++= Seq(
     15       "-language:reflectiveCalls",
     16       "-deprecation",
     17       "-feature",
     18       "-Xcheckinit",
     19       "-Ymacro-annotations",
     20     ),
     21     addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full),
     22   )