perilus

commit fd7229b1df727f251da6041c766492bba30eb042
parent 176dfe4390fc6d41eb880dcfad670c0cde3cb049
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Wed, 28 Jan 2026 21:21:19 -0500

Fix register file tests

Diffstat:
M
src/test/scala/perilus/registerFile.scala
 | 
6
++++--

1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/test/scala/perilus/registerFile.scala b/src/test/scala/perilus/registerFile.scala
@@ -3,14 +3,16 @@ package com.rinthyAi.perilus.test.registerFile
 import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import org.scalatest.funspec.AnyFunSpec
+import scala.collection.mutable.ArrayBuffer
 
 import com.rinthyAi.perilus.registerFile._
+import com.rinthyAi.perilus.test.utils.TestUtils.initMemFile
 
 class RegisterFileTests extends AnyFunSpec with ChiselSim {
   describe("RegisterFile") {
     it("stores and retrieves data") {
       simulate(
-        new RegisterFile(32.W, System.getProperty("user.dir") + "/assets/reg-zeros-x32.hex")
+        new RegisterFile(32.W, initMemFile(ArrayBuffer.fill(32)(0x00000000)))
       ) { registerFile =>
         {
           val reg1 = 5.U
@@ -49,7 +51,7 @@ class RegisterFileTests extends AnyFunSpec with ChiselSim {
     }
     it("doesn't write to x0") {
       simulate(
-        new RegisterFile(32.W, System.getProperty("user.dir") + "/assets/reg-zeros-x32.hex")
+        new RegisterFile(32.W, initMemFile(ArrayBuffer.fill(32)(0x00000000)))
       ) { registerFile =>
         {
           registerFile.io.a3.poke(0.U)