perilus

commit d0b8e7209bf46d7e010fc4b1ae861d7ba80340b6
parent 1c499b6de3e473aa0b0019e1969778911a50f56d
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Tue, 27 Jan 2026 21:05:21 -0500

Run formatter

Diffstat:
M
src/test/scala/perilus/main.scala
 | 
170
++++++++++++++++++++++++++++++++++++++++----------------------------------------

1 file changed, 85 insertions(+), 85 deletions(-)
diff --git a/src/test/scala/perilus/main.scala b/src/test/scala/perilus/main.scala
@@ -7,91 +7,91 @@ import com.rinthyAi.perilus.main._
 
 class PerilusTests extends AnyFunSpec with ChiselSim {
   describe("Perilus") {
-       it("executes lw") {
-         simulate(
-           new Perilus(
-             initRegs = System.getProperty("user.dir") + "/assets/reg-lw-x32.hex",
-             initMem = System.getProperty("user.dir") + "/assets/mem-lw-64x32.hex",
-             withDebug = true
-           )
-         ) { perilus =>
-           {
-             val perilusDebug = perilus.io.debug.get
-
-             // lw x21, 0xa8(x11)
-             val rd = 21
-             val rs1 = 11
-             val base = 0x30
-             val imm = 0xa8
-             val memAddr = (base + imm).U
-             val memData = 0x0f3f9400
-
-             // rs1 contains the base pointer
-             perilusDebug.reg.poke(rs1)
-             perilusDebug.regData.expect(base)
-
-             // rd is empty
-             perilusDebug.reg.poke(rd)
-             perilusDebug.regData.expect(0.U)
-
-             // memAddr contains memData
-             perilusDebug.memAddr.poke(memAddr)
-             perilusDebug.memData.expect(memData)
-
-             // execute the instruction
-             perilus.clock.step(5)
-
-             // rd contains memData
-             perilusDebug.reg.poke(rd)
-             perilusDebug.regData.expect(memData)
-
-             // contents of memAddr have not changed
-             perilusDebug.memAddr.poke(memAddr)
-             perilusDebug.memData.expect(memData)
-           }
-         }
-       }
-       it("executes sw") {
-         simulate(
-           new Perilus(
-             initRegs = System.getProperty("user.dir") + "/assets/reg-sw-x32.hex",
-             initMem = System.getProperty("user.dir") + "/assets/mem-sw-64x32.hex",
-             withDebug = true
-           )
-         ) { perilus =>
-           {
-             val perilusDebug = perilus.io.debug.get
-
-             // sw x6, -4(x9)
-             // sw rs2, imm(rs1)
-             val rs2 = 6
-             val rs1 = 9
-             val base = 0x38
-             val imm = -4
-             val memAddr = (base + imm).U
-             val memData = 0x01830169
-
-             // rs1 contains the base pointer
-             perilusDebug.reg.poke(rs1)
-             perilusDebug.regData.expect(base)
-
-             // rs2 contains data to be stored
-             perilusDebug.reg.poke(rs2)
-             perilusDebug.regData.expect(memData)
-
-             // memAddr doesn't have memData yet
-             perilusDebug.memAddr.poke(memAddr)
-             assert(perilusDebug.memData.peek().litValue != memData)
-
-             // execute the instruction
-             perilus.clock.step(4)
-
-             // contents of memAddr have not changed
-             perilusDebug.memAddr.poke(memAddr)
-             perilusDebug.memData.expect(memData)
-           }
-         }
-       }
+    it("executes lw") {
+      simulate(
+        new Perilus(
+          initRegs = System.getProperty("user.dir") + "/assets/reg-lw-x32.hex",
+          initMem = System.getProperty("user.dir") + "/assets/mem-lw-64x32.hex",
+          withDebug = true
+        )
+      ) { perilus =>
+        {
+          val perilusDebug = perilus.io.debug.get
+
+          // lw x21, 0xa8(x11)
+          val rd = 21
+          val rs1 = 11
+          val base = 0x30
+          val imm = 0xa8
+          val memAddr = (base + imm).U
+          val memData = 0x0f3f9400
+
+          // rs1 contains the base pointer
+          perilusDebug.reg.poke(rs1)
+          perilusDebug.regData.expect(base)
+
+          // rd is empty
+          perilusDebug.reg.poke(rd)
+          perilusDebug.regData.expect(0.U)
+
+          // memAddr contains memData
+          perilusDebug.memAddr.poke(memAddr)
+          perilusDebug.memData.expect(memData)
+
+          // execute the instruction
+          perilus.clock.step(5)
+
+          // rd contains memData
+          perilusDebug.reg.poke(rd)
+          perilusDebug.regData.expect(memData)
+
+          // contents of memAddr have not changed
+          perilusDebug.memAddr.poke(memAddr)
+          perilusDebug.memData.expect(memData)
+        }
+      }
+    }
+    it("executes sw") {
+      simulate(
+        new Perilus(
+          initRegs = System.getProperty("user.dir") + "/assets/reg-sw-x32.hex",
+          initMem = System.getProperty("user.dir") + "/assets/mem-sw-64x32.hex",
+          withDebug = true
+        )
+      ) { perilus =>
+        {
+          val perilusDebug = perilus.io.debug.get
+
+          // sw x6, -4(x9)
+          // sw rs2, imm(rs1)
+          val rs2 = 6
+          val rs1 = 9
+          val base = 0x38
+          val imm = -4
+          val memAddr = (base + imm).U
+          val memData = 0x01830169
+
+          // rs1 contains the base pointer
+          perilusDebug.reg.poke(rs1)
+          perilusDebug.regData.expect(base)
+
+          // rs2 contains data to be stored
+          perilusDebug.reg.poke(rs2)
+          perilusDebug.regData.expect(memData)
+
+          // memAddr doesn't have memData yet
+          perilusDebug.memAddr.poke(memAddr)
+          assert(perilusDebug.memData.peek().litValue != memData)
+
+          // execute the instruction
+          perilus.clock.step(4)
+
+          // contents of memAddr have not changed
+          perilusDebug.memAddr.poke(memAddr)
+          perilusDebug.memData.expect(memData)
+        }
+      }
+    }
     it("executes beq") {
       simulate(
         new Perilus(