commit 1c499b6de3e473aa0b0019e1969778911a50f56d
parent 96a96ed223967caaf5d896b312a457807a84aeee
Author: Bradley Gannon <bradley@bradleygannon.com>
Date: Tue, 27 Jan 2026 21:04:17 -0500
Fix and uncomment existing instruction tests
Diffstat:
4 files changed, 92 insertions(+), 88 deletions(-)
diff --git a/assets/mem-lw-64x32.hex b/assets/mem-lw-64x32.hex
@@ -1,4 +1,4 @@
-02a5aa83
+0a85aa83
b88829b6
5ee7809a
947924f4
diff --git a/assets/reg-lw-x32.hex b/assets/reg-lw-x32.hex
@@ -9,7 +9,7 @@
00000000
00000000
00000000
-0000000c
+00000030
00000000
00000000
00000000
diff --git a/assets/reg-sw-x32.hex b/assets/reg-sw-x32.hex
@@ -7,7 +7,7 @@
01830169
00000000
00000000
-0000003a
+00000038
00000000
00000000
00000000
diff --git a/src/test/scala/perilus/main.scala b/src/test/scala/perilus/main.scala
@@ -7,87 +7,91 @@ import com.rinthyAi.perilus.main._
class PerilusTests extends AnyFunSpec with ChiselSim {
describe("Perilus") {
- // it("executes lw") {
- // simulate(
- // new Perilus(
- // initRegs = System.getProperty("user.dir") + "/assets/reg-lw-x32.hex",
- // initMem = System.getProperty("user.dir") + "/assets/mem-lw-64x32.hex",
- // withDebug = true
- // )
- // ) { perilus =>
- // {
- // val perilusDebug = perilus.io.debug.get
-
- // // lw x21, 0x2a(x11)
- // val rd = 21
- // val rs1 = 11
- // val base = 0xc
- // val imm = 0x2a
- // val memAddr = (base + imm).U
- // val memData = 0x0f3f9400
-
- // // rs1 contains the base pointer
- // perilusDebug.reg.poke(rs1)
- // perilusDebug.regData.expect(base)
-
- // // rd is empty
- // perilusDebug.reg.poke(rd)
- // perilusDebug.regData.expect(0.U)
-
- // // memAddr contains memData
- // perilusDebug.memAddr.poke(memAddr)
- // perilusDebug.memData.expect(memData)
-
- // // execute the instruction
- // perilus.clock.step(6)
-
- // // rd contains memData
- // perilusDebug.reg.poke(rd)
- // perilusDebug.regData.expect(memData)
-
- // // contents of memAddr have not changed
- // perilusDebug.memAddr.poke(memAddr)
- // perilusDebug.memData.expect(memData)
- // }
- // }
- // }
- // it("executes sw") {
- // simulate(
- // new Perilus(
- // initRegs = System.getProperty("user.dir") + "/assets/reg-sw-x32.hex",
- // initMem = System.getProperty("user.dir") + "/assets/mem-sw-64x32.hex",
- // withDebug = true
- // )
- // ) { perilus =>
- // {
- // val perilusDebug = perilus.io.debug.get
-
- // // sw x6, -4(x9)
- // // sw rs2, imm(rs1)
- // val rs2 = 6
- // val rs1 = 9
- // val base = 0x3a
- // val imm = -4
- // val memAddr = (base + imm).U
- // val memData = 0x01830169
-
- // // rs1 contains the base pointer
- // perilusDebug.reg.poke(rs1)
- // perilusDebug.regData.expect(base)
-
- // // rs2 contains data to be stored
- // perilusDebug.reg.poke(rs2)
- // perilusDebug.regData.expect(memData)
-
- // // execute the instruction
- // perilus.clock.step(5)
-
- // // contents of memAddr have not changed
- // perilusDebug.memAddr.poke(memAddr)
- // perilusDebug.memData.expect(memData)
- // }
- // }
- // }
+ it("executes lw") {
+ simulate(
+ new Perilus(
+ initRegs = System.getProperty("user.dir") + "/assets/reg-lw-x32.hex",
+ initMem = System.getProperty("user.dir") + "/assets/mem-lw-64x32.hex",
+ withDebug = true
+ )
+ ) { perilus =>
+ {
+ val perilusDebug = perilus.io.debug.get
+
+ // lw x21, 0xa8(x11)
+ val rd = 21
+ val rs1 = 11
+ val base = 0x30
+ val imm = 0xa8
+ val memAddr = (base + imm).U
+ val memData = 0x0f3f9400
+
+ // rs1 contains the base pointer
+ perilusDebug.reg.poke(rs1)
+ perilusDebug.regData.expect(base)
+
+ // rd is empty
+ perilusDebug.reg.poke(rd)
+ perilusDebug.regData.expect(0.U)
+
+ // memAddr contains memData
+ perilusDebug.memAddr.poke(memAddr)
+ perilusDebug.memData.expect(memData)
+
+ // execute the instruction
+ perilus.clock.step(5)
+
+ // rd contains memData
+ perilusDebug.reg.poke(rd)
+ perilusDebug.regData.expect(memData)
+
+ // contents of memAddr have not changed
+ perilusDebug.memAddr.poke(memAddr)
+ perilusDebug.memData.expect(memData)
+ }
+ }
+ }
+ it("executes sw") {
+ simulate(
+ new Perilus(
+ initRegs = System.getProperty("user.dir") + "/assets/reg-sw-x32.hex",
+ initMem = System.getProperty("user.dir") + "/assets/mem-sw-64x32.hex",
+ withDebug = true
+ )
+ ) { perilus =>
+ {
+ val perilusDebug = perilus.io.debug.get
+
+ // sw x6, -4(x9)
+ // sw rs2, imm(rs1)
+ val rs2 = 6
+ val rs1 = 9
+ val base = 0x38
+ val imm = -4
+ val memAddr = (base + imm).U
+ val memData = 0x01830169
+
+ // rs1 contains the base pointer
+ perilusDebug.reg.poke(rs1)
+ perilusDebug.regData.expect(base)
+
+ // rs2 contains data to be stored
+ perilusDebug.reg.poke(rs2)
+ perilusDebug.regData.expect(memData)
+
+ // memAddr doesn't have memData yet
+ perilusDebug.memAddr.poke(memAddr)
+ assert(perilusDebug.memData.peek().litValue != memData)
+
+ // execute the instruction
+ perilus.clock.step(4)
+
+ // contents of memAddr have not changed
+ perilusDebug.memAddr.poke(memAddr)
+ perilusDebug.memData.expect(memData)
+ }
+ }
+ }
it("executes beq") {
simulate(
new Perilus(
@@ -117,20 +121,20 @@ class PerilusTests extends AnyFunSpec with ChiselSim {
var pc_t = perilus.io.pc.peek()
// execute the first beq instruction:fe64ae23
// beq x3, x6, 0x4
- perilus.clock.step(4)
+ perilus.clock.step(3)
// pc should be at address 1 because x3 != x6
val expected_1 = pc_t.litValue + 4
- // perilus.io.pc.expect(expected_1.U)
+ perilus.io.pc.expect(expected_1.U)
pc_t = perilus.io.pc.peek()
// execute the second beq instruction:
// beq x6, x9, 0x4
- perilus.clock.step(4)
+ perilus.clock.step(3)
// pc should be at address 5 because x6 == x9
val expected_2 = pc_t.litValue + offset.litValue
- // perilus.io.pc.expect(expected_2.U)
+ perilus.io.pc.expect(expected_2.U)
}
}
}
