perilus

commit bab30f16e00b59bae6180491fb5bf5defe223709
parent 93c313d88156c339e9e92434bcaca2c2cda0c76d
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Wed, 22 Jul 2026 18:48:20 -0400

Improve justfile

- Rename test-official to test-act
- Add staleness checks to chisel and verilate so builds get skipped if
  they're already up to date
- Also add force flag to both so the staleness checks can be overriden
- Add build-sim to as a dependency of test-act

Diffstat:
M
.gitignore
 | 
1
+
M
justfile
 | 
65
+++++++++++++++++++++++++++++++++++++++++------------------------

2 files changed, 42 insertions(+), 24 deletions(-)
diff --git a/.gitignore b/.gitignore
@@ -9,6 +9,7 @@
 .scala-build/
 build/
 filelist.f
+generated/
 project/metals.sbt
 project/project/
 project/target/
diff --git a/justfile b/justfile
@@ -1,42 +1,59 @@
-ci: fmt clean test doc
+ci: fmt clean test-chisel doc
 
-test: test-chisel test-official
+test: test-chisel test-act
 
 test-chisel:
     sbt test
 
-test-official:
+test-act: build-sim
     cd riscv-arch-test && \
         CONFIG_FILES=../tests/perilus/test_config.yaml \
         WORKDIR=../tests \
         make --jobs $(nproc)
-    # TODO run the tests in the simulator
+    cd tests && ./run.sh
 
 doc:
     typst compile -f svg doc/perilus.typ
 
 fmt:
     sbt scalafmtAll
-    cd sim && cargo fmt
-
-chisel:
-    sbt run
-
-verilate:
-    verilator --build --public-flat-rw --Mdir verilated --cc \
-        generated/Perilus.sv \
-        generated/Memory.sv \
-        generated/RegisterFile.sv \
-        generated/Alu.sv \
-        generated/ControlUnit.sv \
-        generated/ExtendUnit.sv \
-        generated/AluDecoder.sv \
-        generated/InstructionDecoder.sv \
-        generated/registerFile_32x32.sv \
-        generated/memory_1024x32.sv
-
-simulate:
-    cd sim && cargo run
+    cd sim && cargo fmt && cargo clippy
+
+[script]
+[arg("force", long="force", value="1")]
+chisel force='':
+    if [ -n "{{force}}" ] || [ $(find src/main/ -name "**.scala" -newer "generated/.timestamp" 2>&1 | wc -l) != 0 ]; then
+        sbt run
+        touch generated/.timestamp
+    else
+        echo "Chisel generated output appears to be up to date, skipping"
+    fi
+
+[script]
+[arg("force", long="force", value="1")]
+verilate force='':
+    if [ -n "{{force}}" ] || [ $(find generated/ -name "**.sv" -newer "verilated/.timestamp" 2>&1 | wc -l) != 0 ]; then
+        verilator --build --public-flat-rw --Mdir verilated --cc \
+            generated/Perilus.sv \
+            generated/Memory.sv \
+            generated/RegisterFile.sv \
+            generated/Alu.sv \
+            generated/ControlUnit.sv \
+            generated/ExtendUnit.sv \
+            generated/AluDecoder.sv \
+            generated/InstructionDecoder.sv \
+            generated/registerFile_32x32.sv \
+            generated/memory_1048576x32.sv
+        touch verilated/.timestamp
+    else
+        echo "Verilated output appears to be up to date, skipping"
+    fi
+
+build-sim: chisel verilate
+    cd sim && cargo build --release
+
+simulate: chisel verilate
+    cd sim && cargo run --release
 
 clean:
     sbt clean