justfile (1836B)
1 ci: fmt clean test-chisel doc 2 3 test: test-chisel test-act 4 5 test-chisel: 6 sbt test 7 8 test-act: build-sim 9 cd riscv-arch-test && \ 10 CONFIG_FILES=../tests/perilus/test_config.yaml \ 11 WORKDIR=../tests \ 12 make --jobs $(nproc) 13 cd tests && ./run.sh 14 15 doc: 16 typst compile -f svg doc/perilus.typ 17 18 fmt: 19 sbt scalafmtAll 20 cd sim && cargo fmt --all && cargo clippy --workspace --all-targets 21 22 [script] 23 [arg("force", long="force", value="1")] 24 chisel force='': 25 if [ -n "{{force}}" ] || [ $(find src/main/ -name "**.scala" -newer "generated/.timestamp" 2>&1 | wc -l) != 0 ]; then 26 sbt run 27 touch generated/.timestamp 28 else 29 echo "Chisel generated output appears to be up to date, skipping" 30 fi 31 32 [script] 33 [arg("force", long="force", value="1")] 34 verilate force='': 35 if [ -n "{{force}}" ] || [ $(find generated/ -name "**.sv" -newer "verilated/.timestamp" 2>&1 | wc -l) != 0 ]; then 36 verilator --build --trace-vcd --public-flat-rw --Mdir verilated --cc \ 37 generated/Perilus.sv \ 38 generated/Memory.sv \ 39 generated/RegisterFile.sv \ 40 generated/Alu.sv \ 41 generated/ControlUnit.sv \ 42 generated/ExtendUnit.sv \ 43 generated/AluDecoder.sv \ 44 generated/InstructionDecoder.sv \ 45 generated/registerFile_32x32.sv \ 46 generated/memory_1048576x32.sv 47 touch verilated/.timestamp 48 else 49 echo "Verilated output appears to be up to date, skipping" 50 fi 51 52 build-sim: chisel verilate 53 cd sim && cargo build --release -p sim-cli 54 55 simulate: chisel verilate 56 cd sim && cargo run --release -p sim-gui 57 58 clean: 59 sbt clean 60 rm -rf build generated verilated 61 cd sim && cargo clean 62 rm -rf tests/perilus-rv32i tests/stamps 63 cd riscv-arch-test && make clean