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commit 2a60eae4eae580443792e072aa31c1df80c5d388
parent f8f8f5ab9fe2d59a0cf4a37eb15a37309e512041
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Thu,  2 Apr 2026 20:24:57 -0400

Only write data to registers or memory when reset is not asserted

Diffstat:
M
src/main/scala/memory.scala
 | 
2
+-
M
src/main/scala/registerFile.scala
 | 
2
+-

2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/main/scala/memory.scala b/src/main/scala/memory.scala
@@ -35,7 +35,7 @@ class Memory(
     d.memData := memory.read(d.memAddr >> AddressShift)
   })
 
-  when(io.writeEnable) {
+  when(io.writeEnable && !reset.asBool) {
     memory.write(io.address >> AddressShift, io.writeData & io.dataMask.asUInt)
   }
 
diff --git a/src/main/scala/registerFile.scala b/src/main/scala/registerFile.scala
@@ -29,7 +29,7 @@ class RegisterFile(width: Width, initRegs: String = "", withDebug: Boolean = fal
   io.rd1 := registerFile.read(io.a1)
   io.rd2 := registerFile.read(io.a2)
 
-  when(io.writeEnable3 && io.a3 =/= 0.U) {
+  when(io.writeEnable3 && io.a3 =/= 0.U && !reset.asBool) {
     registerFile.write(io.a3, io.writeData3)
   }
 }