perilus

commit 19e57583faaf31adaec537c7c56993ca7d82c285
parent 48947a97d97b6f0cc401aed5fb203c98f240d701
Author: mbbutler <m.brady.butler@gmail.com>
Date:   Fri,  2 Jan 2026 14:25:48 -0500

Add 'sw' test and 'just' project mgmt

Diffstat:
A
.vscode/settings.json
 | 
6
++++++
M
README.md
 | 
4
+++-
A
assets/mem-sw-64x32.hex
 | 
64
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
A
assets/reg-sw-x32.hex
 | 
32
++++++++++++++++++++++++++++++++
A
justfile
 | 
11
+++++++++++
M
shell.nix
 | 
1
+
M
src/test/scala/perilus/main.scala
 | 
37
+++++++++++++++++++++++++++++++++++++

7 files changed, 154 insertions(+), 1 deletion(-)
diff --git a/.vscode/settings.json b/.vscode/settings.json
@@ -0,0 +1,5 @@
+{
+    "files.watcherExclude": {
+        "**/target": true
+    }
+}+
\ No newline at end of file
diff --git a/README.md b/README.md
@@ -16,11 +16,13 @@ multi-cycle processor from [Harris and Harris].
     - [Scala 2] (**not 3** because Chisel isn't compatible with it)
     - [`sbt`][sbt]
     - [Verilator]
-1. `sbt test`
+    - [`just`][just]
+1. `just test`
 
 [Scala 2]: https://www.scala-lang.org/download/all.html
 [sbt]: https://www.scala-sbt.org/
 [Verilator]: https://verilator.org/guide/latest/overview.html
+[just]: https://github.com/casey/just
 
 [^nix]: If you use the `nix` package manager, you can use the `shell.nix` file in the project root
     with `nix-shell`.
diff --git a/assets/mem-sw-64x32.hex b/assets/mem-sw-64x32.hex
@@ -0,0 +1,64 @@
+fe64ae23
+b88829b6
+5ee7809a
+947924f4
+fc24525a
+6c858974
+4996dd8c
+50415755
+b329e2c1
+99a84ca8
+ca029ae4
+a57954e9
+a7b0a4b1
+5f1c57ea
+bab5ee54
+e63aec6d
+7afaad60
+334c7d51
+bc83bea3
+63b83aab
+e1940fda
+4812b9fa
+7c224e0a
+305c08cc
+85e21635
+6e0cd50c
+d976069b
+f7f1ab0f
+24d8e524
+0f15069c
+1fa3eed3
+f73d90fa
+bd46aca5
+a519ad77
+70cd4ed3
+a722ba58
+cec41109
+9955f8a8
+ba5eb4f8
+cb32fd9d
+4f3fc791
+43bcbe26
+c1600d35
+0b5fc381
+dddfa0c3
+0331db73
+1e088fee
+9a0cdee4
+29580f62
+043925f7
+653647af
+d5e9eb13
+3e559887
+f098fa6f
+0f3f9400
+07163d81
+b37a3f8e
+0c11b791
+b3fa9fcf
+9d6ae141
+a34ef0d5
+3e850e1a
+2a410325
+8fce4057
diff --git a/assets/reg-sw-x32.hex b/assets/reg-sw-x32.hex
@@ -0,0 +1,32 @@
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+01830169
+00000000
+00000000
+0000003a
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
diff --git a/justfile b/justfile
@@ -0,0 +1,10 @@
+ci: fmt clean test
+
+test:
+    sbt test
+
+fmt:
+    sbt scalafmtAll
+
+clean:
+    sbt clean+
\ No newline at end of file
diff --git a/shell.nix b/shell.nix
@@ -8,6 +8,7 @@ pkgs.mkShellNoCC {
     act
     coursier
     jdk21
+    just
     metals
     sbt
     verilator
diff --git a/src/test/scala/perilus/main.scala b/src/test/scala/perilus/main.scala
@@ -51,5 +51,42 @@ class PerilusTests extends AnyFunSpec with ChiselSim {
         }
       }
     }
+    it("executes sw") {
+      simulate(
+        new Perilus(
+          initRegs = System.getProperty("user.dir") + "/assets/reg-sw-x32.hex",
+          initMem = System.getProperty("user.dir") + "/assets/mem-sw-64x32.hex",
+          withDebug = true
+        )
+      ) { perilus =>
+        {
+          val perilusDebug = perilus.io.debug.get
+
+          // sw x6, -4(x9)
+          // sw rs2, imm(rs1)
+          val rs2 = 6
+          val rs1 = 9
+          val base = 0x3a
+          val imm = -4
+          val memAddr = (base + imm).U
+          val memData = 0x01830169
+
+          // rs1 contains the base pointer
+          perilusDebug.reg.poke(rs1)
+          perilusDebug.regData.expect(base)
+
+          // rs2 contains data to be stored
+          perilusDebug.reg.poke(rs2)
+          perilusDebug.regData.expect(memData)
+
+          // execute the instruction
+          perilus.clock.step(5)
+
+          // contents of memAddr have not changed
+          perilusDebug.memAddr.poke(memAddr)
+          perilusDebug.memData.expect(memData)
+        }
+      }
+    }
   }
 }