perilus

commit c5b29792d9ae5274104669c7a66e41796729d52a
parent 8f2ef935b4cc261cc4aaac8aebfb6385ce7cffc6
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Wed, 22 Jul 2026 17:54:51 -0400

Tweak processor model config and simplify pass/fail macros

Diffstat:
M
tests/perilus/perilus.yaml
 | 
67
++++++++++++++++++++++++++++++-------------------------------------
M
tests/perilus/rvmodel_macros.h
 | 
26
+++++++-------------------

2 files changed, 37 insertions(+), 56 deletions(-)
diff --git a/tests/perilus/perilus.yaml b/tests/perilus/perilus.yaml
@@ -7,47 +7,40 @@ name: perilus-rv32i
 description: Perilus RISC-V processor
 implemented_extensions:
   - { name: I, version: "= 2.1" }
-  - { name: M, version: "= 2.0" }
   - { name: Sm, version: "= 1.12.0" }
 params:
   MXLEN: 32
-  PRECISE_SYNCHRONOUS_EXCEPTIONS: true
-  TRAP_ON_ECALL_FROM_M: true
-  TRAP_ON_EBREAK: true
-  MARCHID_IMPLEMENTED: true
-  ARCH_ID_VALUE: 1
-  MIMPID_IMPLEMENTED: true
-  IMP_ID_VALUE: 0x0
-  VENDOR_ID_BANK: 0x0
-  VENDOR_ID_OFFSET: 0x0
+  CONFIG_PTR_ADDRESS: 0
+  HPM_COUNTER_EN: [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
+  MARCHID_IMPLEMENTED: false
+  MCOUNTENABLE_EN: [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
+  MCOUNTINHIBIT_IMPLEMENTED: false
+  MIMPID_IMPLEMENTED: false
   MISALIGNED_LDST: false
   MISALIGNED_LDST_EXCEPTION_PRIORITY: high
-  TRAP_ON_ILLEGAL_WLRL: false
-  TRAP_ON_UNIMPLEMENTED_INSTRUCTION: true
-  TRAP_ON_RESERVED_INSTRUCTION: true
-  TRAP_ON_UNIMPLEMENTED_CSR: true
-  REPORT_VA_IN_MTVAL_ON_BREAKPOINT: true
-  REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED: true
-  REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED: true
-  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED: true
-  REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: true
-  REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: true
-  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: true
-  REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: true
-  MTVAL_WIDTH: 32
-  CONFIG_PTR_ADDRESS: 0
-  PMA_GRANULARITY: 3
-  PHYS_ADDR_WIDTH: 32
-  M_MODE_ENDIANNESS: little
-  MISA_CSR_IMPLEMENTED: true
-  MTVEC_ACCESS: rw
-  MTVEC_MODES: [0, 1]
-  MTVEC_BASE_ALIGNMENT_DIRECT: 4
-  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MISA_CSR_IMPLEMENTED: false
+  MTVAL_WIDTH: 0
+  MTVEC_ACCESS: ro
   MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
+  MTVEC_MODES: [0]
+  M_MODE_ENDIANNESS: little
   NUM_PMP_ENTRIES: 0
-  MUTABLE_MISA_M: false
-  MCOUNTINHIBIT_IMPLEMENTED: true
-  MCOUNTENABLE_EN: [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
-  HPM_COUNTER_EN: [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
-  COUNTINHIBIT_EN: [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
+  PHYS_ADDR_WIDTH: 32
+  PMA_GRANULARITY: 3
+  PRECISE_SYNCHRONOUS_EXCEPTIONS: true
+  REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: false
+  REPORT_VA_IN_MTVAL_ON_BREAKPOINT: false
+  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: false
+  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED: false
+  REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: false
+  REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED: false
+  REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: false
+  REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED: false
+  TRAP_ON_EBREAK: false
+  TRAP_ON_ECALL_FROM_M: false
+  TRAP_ON_ILLEGAL_WLRL: false
+  TRAP_ON_RESERVED_INSTRUCTION: false
+  TRAP_ON_UNIMPLEMENTED_CSR: false
+  TRAP_ON_UNIMPLEMENTED_INSTRUCTION: false
+  VENDOR_ID_BANK: 0x0
+  VENDOR_ID_OFFSET: 0x0
diff --git a/tests/perilus/rvmodel_macros.h b/tests/perilus/rvmodel_macros.h
@@ -1,27 +1,15 @@
 #ifndef _RVMODEL_MACROS_H
 #define _RVMODEL_MACROS_H
 
-#define RVMODEL_DATA_SECTION \
-        .pushsection .tohost,"aw",@progbits;                \
-        .balign 8; .global tohost; tohost: .word 0;         \
-        .balign 8; .global fromhost; fromhost: .word 0;     \
-        .popsection
-
-#define RVMODEL_HALT_PASS  \
-  li x1, 1;                \
-  la t0, tohost;           \
-  write_tohost_pass:       \
-    sw x1, 0(t0);          \
-    sw x0, 4(t0);          \
-    j write_tohost_pass;    \
+#define RVMODEL_DATA_SECTION
+
+#define RVMODEL_HALT_PASS \
+  li x1, 0xebbb3689;      \
+  ebreak;
 
 #define RVMODEL_HALT_FAIL \
-  li x1, 3;                \
-  la t0, tohost;           \
-  write_tohost_fail:       \
-    sw x1, 0(t0);          \
-    sw x0, 4(t0);          \
-    j write_tohost_fail;    \
+  li x1, 0xd02a545a;      \
+  ebreak;
 
 #define RVMODEL_IO_WRITE_STR(_R1, _R2, _R3, _STR_PTR)