perilus

commit ad41caa65641049219432f45c0dca84337261018
parent 0b093e9636dc898fde5f065585db4918f73b4dfe
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Mon,  1 Dec 2025 19:16:52 -0500

Connect data path and control unit IO

Diffstat:
M
src/main/scala/controlUnit.scala
 | 
2
+-
M
src/main/scala/main.scala
 | 
88
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------

2 files changed, 72 insertions(+), 18 deletions(-)
diff --git a/src/main/scala/controlUnit.scala b/src/main/scala/controlUnit.scala
@@ -7,7 +7,7 @@ class ControlUnit extends Module {
   val io = IO(new Bundle {
     val op = Input(UInt(7.W))
     val funct3 = Input(UInt(3.W))
-    val funct7 = Input(Bool())
+    val funct7_5 = Input(Bool())
 
     val adrSrc, branch, irWrite, memWrite, pcUpdate, pcWrite, regWrite = Output(Bool())
     val aluSrcA, aluSrcB, aluOp, immSrc, resultSrc = Output(UInt(2.W))
diff --git a/src/main/scala/main.scala b/src/main/scala/main.scala
@@ -28,28 +28,82 @@ class Perilus extends Module {
   val memory = Module(new Memory(memorySizeWords, width))
   val registerFile = Module(new RegisterFile(width))
 
-  // TODO connect inputs and outputs
+  val pc = RegInit(0.U(width))
+  val pcNext = WireDefault(UInt(width), 0.U)
+  when(controlUnit.io.pcWrite) {
+    pc := pcNext
+  }
 
-  alu.io.aluControl := 0.U
-  alu.io.srcA := 0.U
-  alu.io.srcB := 0.U
+  val oldPc = RegInit(0.U(width))
+  when(controlUnit.io.irWrite) {
+    oldPc := pc
+  }
 
-  controlUnit.io.op := 0.U
-  controlUnit.io.funct3 := 0.U
-  controlUnit.io.funct7 := 0.U
+  val instr = RegInit(0.U(width))
+  when(controlUnit.io.irWrite) {
+    instr := memory.io.readData
+  }
 
-  extendUnit.io.input := 0.U
-  extendUnit.io.immSrc := 0.U
+  val readDataBuf = RegInit(0.U(width))
+  readDataBuf := memory.io.readData
 
-  memory.io.address := 0.U
-  memory.io.writeData := 0.U
-  memory.io.writeEnable := 0.U
+  val rd1Buf = RegInit(0.U(width))
+  rd1Buf := registerFile.io.rd1
+  val rd2Buf = RegInit(0.U(width))
+  rd2Buf := registerFile.io.rd2
 
-  registerFile.io.a1 := 0.U
-  registerFile.io.a2 := 0.U
-  registerFile.io.a3 := 0.U
-  registerFile.io.writeData3 := 0.U
-  registerFile.io.writeEnable3 := false.B
+  val aluOutBuf = RegInit(0.U(width))
+  aluOutBuf := alu.io.aluResult
+
+  val result = WireDefault(0.U(width))
+  when(controlUnit.io.resultSrc === "b00".U) {
+    result := aluOutBuf
+  }.elsewhen(controlUnit.io.resultSrc === "b01".U) {
+    result := readDataBuf
+  }.elsewhen(controlUnit.io.resultSrc === "b10".U) {
+    result := alu.io.aluResult
+  }
+
+  alu.io.aluControl := controlUnit.io.aluControl
+  when(controlUnit.io.aluSrcA === "b00".U) {
+    alu.io.srcA := pc
+  }.elsewhen(controlUnit.io.aluSrcA === "b01".U) {
+    alu.io.srcA := oldPc
+  }.elsewhen(controlUnit.io.aluSrcA === "b10".U) {
+    alu.io.srcA := rd1Buf
+  }.otherwise {
+    alu.io.srcA := 0.U
+  }
+  when(controlUnit.io.aluSrcB === "b00".U) {
+    alu.io.srcB := rd2Buf
+  }.elsewhen(controlUnit.io.aluSrcB === "b01".U) {
+    alu.io.srcB := extendUnit.io.immExt
+  }.elsewhen(controlUnit.io.aluSrcB === "b10".U) {
+    alu.io.srcB := 4.U
+  }.otherwise {
+    alu.io.srcB := 0.U
+  }
+
+  controlUnit.io.op := instr(6, 0)
+  controlUnit.io.funct3 := instr(14, 12)
+  controlUnit.io.funct7_5 := instr(30)
+
+  extendUnit.io.input := instr(31, 7)
+  extendUnit.io.immSrc := controlUnit.io.immSrc
+
+  when(controlUnit.io.adrSrc) {
+    memory.io.address := result
+  }.otherwise {
+    memory.io.address := pc
+  }
+  memory.io.writeData := rd2Buf
+  memory.io.writeEnable := controlUnit.io.memWrite
+
+  registerFile.io.a1 := instr(19, 15)
+  registerFile.io.a2 := instr(24, 20)
+  registerFile.io.a3 := instr(11, 7)
+  registerFile.io.writeData3 := result
+  registerFile.io.writeEnable3 := controlUnit.io.regWrite
 }
 
 object Perilus extends App {