perilus

commit 796b36980503b2175fbc2ba7a94924ddecca181b
parent 408e06e258422bc402077bff77659bc13a2a2f81
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Fri,  2 Oct 2026 21:57:55 -0400

Mask LSB when writing PC

Diffstat:
M
src/main/scala/main.scala
 | 
3
++-

1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/main/scala/main.scala b/src/main/scala/main.scala
@@ -71,7 +71,8 @@ class Perilus(
   val pc = RegInit(0.U(width))
   val pcNext = WireDefault(UInt(width), 0.U)
   when(controlUnit.io.pcWrite) {
-    pc := pcNext
+    // Mask LSB
+    pc := pcNext & ~1.U(width)
   }
 
   io.pc := pc