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commit 04c8427eaf8d42b9291a0a0c929200f079651f8b
parent 480ff5191f91fbef276086cbd7fd788fdb6d4528
Author: Bradley Gannon <bradley@bradleygannon.com>
Date:   Sun,  4 Oct 2026 12:48:58 -0400

Fix a bug where the data mask was being applied incorrectly

Diffstat:
M
src/main/scala/controlUnit.scala
 | 
4
+++-

1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/main/scala/controlUnit.scala b/src/main/scala/controlUnit.scala
@@ -47,7 +47,9 @@ class ControlUnit(withDebug: Boolean = false) extends Module {
   io.regWrite := false.B
   io.resultSrc := ResultSrc.aluOutBuf
 
-  when(io.op === Opcode.load || io.op === Opcode.store) {
+  when(
+    (state === ControlUnitState.memRead || state === ControlUnitState.memWb || state === ControlUnitState.memWrite) && (io.op === Opcode.load || io.op === Opcode.store)
+  ) {
     when(io.funct3 === 0.U || io.funct3 === 4.U) {
       io.dataMask := DataMask.byte
     }.elsewhen(io.funct3 === 1.U || io.funct3 === 5.U) {