perilus.typ (5747B)
1 #import "@preview/fletcher:0.5.8" as fletcher: diagram, node, edge, shapes.trapezium 2 3 #set page(width: auto, height: auto) 4 5 #let reg(x, y, id) = { 6 node((x, y), raw(id), name: id, stroke: 1pt) 7 } 8 9 #let mux(x, y, id, n) = { 10 let i = 0 11 while i < n { 12 node((x, {y + i}), raw(str(i)), name: id + "_" + str(i)) 13 i += 1 14 } 15 let i = 0 16 let enclose = while i < n { 17 (label(id + "_" + str(i)),) 18 i += 1 19 } 20 node( 21 name: id, 22 enclose: enclose, 23 shape: trapezium.with(dir: right), 24 stroke: 1pt, 25 inset: 0mm, 26 ) 27 } 28 29 #let module(x, y, id, io_ids, width, alignment) = { 30 let io_y = y 31 for io_id in io_ids { 32 let name = id + "_" + io_id 33 node((x, io_y), align(alignment)[#raw(io_id)], name: name, width: width) 34 io_y = io_y + 1 35 } 36 let io_names = for io_id in io_ids { 37 (label(id + "_" + io_id),) 38 } 39 node( 40 enclose: io_names, 41 name: label(id), 42 stroke: 1pt, 43 inset: 0mm, 44 ) 45 } 46 47 #diagram( 48 debug: 0, 49 spacing: (5mm, 1mm), 50 51 module( 52 24, 0, "controlUnit", 53 ("op", "funct3", "funct7-5", "zero", "adrSrc", "irWrite", "memWrite", "pcWrite", "regWrite", 54 "aluSrcA", "aluSrcB", "resultSrc", "immSrc", "aluControl", "dataMask", "lessThan"), 55 23mm, 56 left, 57 ), 58 module(0, 0, "registerFile", ("a1", "a2", "a3", "writeData3", "writeEnable3", "rd1", "rd2"), 27mm, 59 right), 60 module(0, 7, "extendUnit", ("input", "immSrc", "immExt"), 27mm, right), 61 module(0, 10, "memory", ("address", "writeData", "writeEnable", "readData", "dataMask"), 27mm, right), 62 module(0, 15, "alu", ("aluControl", "srcA", "srcB", "aluResult", "zero", "lessThan"), 27mm, right), 63 64 reg(12.5, 16.5, "pc"), 65 reg(14, 16.5, "oldPc"), 66 reg(12, 1, "instr"), 67 reg(8, 16, "readDataBuf"), 68 reg(8, 5, "rd1Buf"), 69 reg(8, 6, "rd2Buf"), 70 reg(8, 7, "four"), 71 reg(8, 15, "aluOutBuf"), 72 73 edge(<controlUnit_pcWrite.west>, (12.5, 7), <pc.north>, "->"), 74 75 edge(<controlUnit_irWrite.west>, (16, 5), (16, 0), (12, 0), <instr.north>, "->"), 76 edge(<pc.east>, <oldPc.west>, "->"), 77 78 edge(<controlUnit_irWrite.west>, (14, 5), <oldPc.north>, "->"), 79 edge(<memory_readData.east>, (7, 13), (7, 1), <instr.west>, "->"), 80 81 edge(<memory_readData.east>, (7, 13), (7, 16), <readDataBuf.west>, "->"), 82 83 edge(<registerFile_rd1.east>, <rd1Buf.west>, "->"), 84 edge(<registerFile_rd2.east>, <rd2Buf.west>, "->"), 85 86 edge(<alu_aluResult.east>, (5, 18), (5, 15), <aluOutBuf.west>, "->"), 87 88 mux(9, 15, "muxResult", 4), 89 edge(<controlUnit_resultSrc.west>, (9, 11), <muxResult.north>, "->"), 90 edge(<muxResult.east>, (10, 16.5), <pc.west>, "->", label: `result`, label-pos: 0.5, label-side: right), 91 edge(<aluOutBuf.east>, <muxResult_0.west>, "->"), 92 edge(<readDataBuf.east>, <muxResult_1.west>, "->"), 93 edge(<alu_aluResult.east>, (5, 18), (5, 17), <muxResult_2.west>, "->"), 94 edge(<extendUnit_immExt.east>, (2, 9), (2, 17.5), (6, 17.5), (6, 18), <muxResult_3.west>, "->"), 95 96 edge(<controlUnit_aluControl.west>, (16, 13), (16, 13.75), (3, 13.75), (3, 15), <alu_aluControl.east>, "->"), 97 98 mux(17, 15.5, "muxAluSrcA", 3), 99 edge(<controlUnit_aluSrcA.west>, (17, 9), <muxAluSrcA.north>, "->"), 100 edge(<muxAluSrcA.east>, (18, 16.5), (18, 18.75), (3, 18.75), (3, 16), <alu_srcA.east>, "->", label: `A`, label-pos: 0.15), 101 edge(<pc.east>, (13, 16.5), (13, 15.5), <muxAluSrcA_0.west>, "->"), 102 edge(<oldPc.east>, <muxAluSrcA_1.west>, "->"), 103 edge(<rd1Buf.east>, (8.5, 5), (8.5, 3.5), (11.5, 3.5), (11.5, 17.5), <muxAluSrcA_2.west>, "->"), 104 105 mux(10, 5, "muxAluSrcB", 3), 106 edge(<controlUnit_aluSrcB.west>, (18, 10), (18, 3), (10, 3), <muxAluSrcB.north>, "->"), 107 edge(<muxAluSrcB.east>, (11, 6), (11, 13.5), (4, 13.5), (4, 17), <alu_srcB.east>, "->", label: `B`, label-pos: 0.15), 108 edge(<rd2Buf.east>, (9, 6), (9, 5), <muxAluSrcB_0.west>, "->"), 109 edge(<extendUnit_immExt.east>, (9.5, 9), (9.5, 6), <muxAluSrcB_1.west>, "->"), 110 edge(<four.east>, <muxAluSrcB_2.west>, "->"), 111 112 edge(<alu_zero.east>, (22, 19), (22, 3), <controlUnit_zero.west>, "->"), 113 edge(<alu_lessThan.east>, (23, 20), (23, 15), <controlUnit_lessThan.west>, "->"), 114 115 edge(<instr.east>, (18, 1), (18, 0), <controlUnit_op.west>, "->", label: `[6:0]`, label-pos: 0.82), 116 edge(<instr.east>, (18, 1), <controlUnit_funct3.west>, "->", label: `[14:12]`, label-pos: 117 0.75), 118 edge(<instr.east>, (18, 1), (18, 2), <controlUnit_funct7-5.west>, "->", label: `[30]`, label-pos: 119 0.82), 120 121 edge(<instr.east>, (14, 1), (14, -1), (5, -1), (5, 7), <extendUnit_input.east>, "->", label: `[31:7]`, label-pos: 0.9), 122 edge(<controlUnit_immSrc.west>, (21, 12), (21, 8), <extendUnit_immSrc.east>, "->"), 123 124 mux(15, 12, "muxMemAddr", 2), 125 edge(<controlUnit_adrSrc.west>, (15, 4), <muxMemAddr.north>, "->"), 126 edge(<muxMemAddr.east>, (16, 12.5), (16, 10), <memory_address.east>, "->"), 127 edge(<muxResult.east>, (10, 16.5), (10, 12), <muxMemAddr_0.west>, "->"), 128 edge(<pc.east>, (13, 16.5), (13, 13), <muxMemAddr_1.west>, "->"), 129 130 edge(<rd2Buf.east>, (8.5, 6), (8.5, 11), <memory_writeData.east>, "->"), 131 edge(<controlUnit_memWrite.west>, (14.5, 6), (14.5, 10.5), (9.5, 10.5), (9.5, 12), <memory_writeEnable.east>, "->"), 132 edge(<controlUnit_dataMask.west>, <memory_dataMask.east>, "->"), 133 134 edge(<instr.east>, (14, 1), (14, -1), (5, -1), (5, 0), <registerFile_a1.east>, "->", label: 135 `[19:15]`, label-pos: 0.9), 136 edge(<instr.east>, (14, 1), (14, -1), (5, -1), (5, 1), <registerFile_a2.east>, "->", label: 137 `[24:20]`, label-pos: 0.9), 138 edge(<instr.east>, (14, 1), (14, -1), (5, -1), (5, 2), <registerFile_a3.east>, "->", label: 139 `[11:7]`, label-pos: 0.9), 140 edge(<muxResult.east>, (10, 16.5), (10, 9.5), (4, 9.5), (4, 3), <registerFile_writeData3.east>, "->"), 141 edge(<controlUnit_regWrite.west>, (23, 8), (23, 4.5), (11, 4.5), (11, 4), <registerFile_writeEnable3.east>, "->"), 142 )